ADC3421 datasheet(46/80 Pages) TI2

46 / 80 page

Frequency (MHz)

-120

-100

-80

-60

-40

-20

D016

Frequency (MHz)

-120

-100

-80

-60

-40

-20

D017

ADC3421, ADC3422, ADC3423, ADC3424

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

www.ti.com

9.4 Device Functional Modes

9.4.1 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a

faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for

operation with a 125-MHz clock and the divide-by-2 option supports a maximum input clock of 250 MHz and the

divide-by-4 option provides a maximum input clock frequency of 500 MHz.

9.4.2 Chopper Functionality

The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC

noise spectrum by shifting the 1/f noise from dc to fS / 2. Figure 139 shows the noise spectrum with the chopper

off and Figure 140 shows the noise spectrum with the chopper on. This function is especially useful in

applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper

can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper

function creates a spur at fS / 2 that must be filtered out digitally.

fS = 125 MSPS, SNR = 70.4 dBFS,

fIN = 10 MHz, SFDR = 98 dBc

fIN = 10 MHz, SFDR = 97 dBc

Figure 139. Chopper Off

Figure 140. Chopper On

9.4.3 Power-Down Control

The power-down functions of the ADC342x can be controlled either through the parallel control pin (PDN) or

through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-

down or standby functionality, as shown in Table 4.

Table 4. Power-Down Modes

FUNCTION

POWER CONSUMPTION (mW)

WAKE-UP TIME (µs)

Global power-down

Standby

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