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ADC3421 Datasheet(PDF) 60 Page - Texas Instruments |
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ADC3421 Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 80 page ![]() ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.18 Register 134h (address = 134h) Figure 164. Register 134h 7 6 5 4 3 2 1 0 0 0 DIS DITH CHA 0 DIS DITH CHA 0 0 0 W-0h W-0h R/W-0h W-0h R/W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 27. Register 134h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0. 5 DIS DITH CHA R/W 0h Set this bit along with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 4 0 W 0h Must write 0. 3 DIS DITH CHA R/W 0h Set this bit along with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 2-0 0 W 0h Must write 0. 9.6.1.19 Register 139h (address = 139h) Figure 165. Register 139h 7 6 5 4 3 2 1 0 0 0 0 0 SP1 CHA 0 0 0 W-0h W-0h W-0h W-0h R/W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 28. Register 139h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0. 3 SP1 CHA R/W 0h This bit sets the special mode for best performance on channel A. Always write 1 after reset. 2-0 0 W 0h Must write 0. 9.6.1.20 Register 21Dh (address = 21Dh) Figure 166. Register 21Dh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 HIGH IF MODE1 0 W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 29. Register 21Dh Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 HIGH IF MODE1 R/W 0h Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. 0 0 W 0h Must write 0. 60 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 |
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