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ADC3421 Datasheet(PDF) 65 Page - Texas Instruments |
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ADC3421 Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 80 page ![]() ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.31 Register 534h (address = 534h) Figure 177. Register 534h 7 6 5 4 3 2 1 0 0 0 DIS DITH CHC 0 DIS DITH CHC 0 0 0 W-0h W-0h R/W-0h W-0h R/W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 40. Register 534h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0. 5 DIS DITH CHC R/W 0h Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 4 0 W 0h Must write 0. 3 DIS DITH CHC R/W 0h Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 2-0 0 W 0h Must write 0. 9.6.1.32 Register 539h (address = 539h) Figure 178. Register 539h 7 6 5 4 3 2 1 0 0 0 0 0 SP1 CHC 0 0 0 W-0h W-0h W-0h W-0h R/W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 41. Register 539h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0. 3 SP1 CHC R/W 0h This bit sets the special mode for best performance on channel C. Always write 1 after reset. 2-0 0 W 0h Must write 0. 9.6.1.33 Register 608h (address = 608h) Figure 179. Register 608h 7 6 5 4 3 2 1 0 HIGH IF MODE<7:6> 0 0 0 0 0 0 W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 42. Register 608h Field Descriptions Bit Field Type Reset Description 7-6 HIGH IF MODE<7:6> R/W 0h Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. 5-0 0 W 0h Must write 0. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 65 Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 |
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