TUSB1210 datasheet(61/72 Pages) TI2

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Table 10-1. TUSB121x USB2.0 Product Family Board Layout Recommendations (continued)

Item

USB General Considerations

2.12

Avoid creating stubs on the DP/DM traces as stubs cause signal reflections and affect global signal quality.

2.13

If stubs are unavoidable, they must be less than 200 mils (≈0.5 cm).

2.14

Route DP/DM signals over continuous VCC or GND planes, without interruption, avoiding crossing anti-etch (plane splits), which increase both inductance and radiation

levels by introducing a greater loop area.

2.15

Route DP/DM signals with at least 25 mils (≈0.65 mm) away from any plane splits.

2.16

Follow the 20×h thumb rule by keeping traces at least 20×(height above the plane) away from the edge of the plane (VCC or GND, depending on the plane the trace is

over).

2.17

Changing signal layers is preferable to crossing plane splits if a choice must be made.

2.18

If crossing a plane split is completely unavoidable, proper placement of stitching capacitors can minimize the adverse effects on EMI and signal quality performance

caused by crossing the split.

2.19

Avoid anti-etch on the ground plane.

ULPI Interface (ULPIDATA<7:0>, ULPICLK, ULPINXT, ULPIDIR, ULPISTP)

3.00

Route ULPI 12-pin bus as a 50 Ω single-ended adapted bus.

3.01

Route ULPI 12-pin bus with minimum trace lengths and a strict maximum of 90 mm, to ensure timing. (Timing budget 600 ps maximum 1-way delay assuming 66 ps/cm.)

3.02

Route ULPI 21-pin bus equalizing paths lengths as much as possible to have equal delays.

3.03

Route ULPI 12-pin bus as clock signals and set a minimum spacing of 3 times the trace width (S < 3W).

3.04

If the 3W minimum spacing is not respected, the minimum spacing for clock signals based on EMI testing experience is 50 mils (1.27 mm).

3.05

Route ULPI 12-pin bus with a dedicated ground plane.

3.06

Place and route the ULPI monitoring buffers as close as possible from the device ULPI bus (on test boards).

USB Clock (USBCLKIN, CLK_IN1, CLK_IN0)

4.00

Route the USB clock with the minimum possible trace length.

4.01

Keep the maximum possible distance between the USB clock and the other platform clocks, power sources, and digital and analog signals.

4.02

Route the USBCLKIN, CLK_IN1 and CLK_IN0 inputs as 50 Ω single-ended signals.

USB Power Supply (VBUS, REG3V3, REG1V5, VBAT)

5.00

VBUS must be a power plane from the device VBUS ball to the USB receptacle, or if a power plan is not possible, VBUS must be as large as possible.

5.01

Power signals must be wide to accommodate current level.

www.ti.com

TUSB1210

SLLSE09J – NOVEMBER 2009 – REVISED JULY 2021

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