DA9213 datasheet(32/62 Pages) RENESAS

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DA9213, DA9214, DA9215 Datasheet

R16DS0598EJ0361 Rev.03.61

Nov 03, 2025

CFR0011-120-00

Page 32

5.3

Operating Modes

5.3.1

ON Mode

DA9213, DA9214, and DA9215 are in ON Mode when the IC_EN port is higher than EN_ON and the supply

voltage is higher than VTH(UVLO)(VDD). Once enabled, the host processor can start the communication with

DA9213, DA9214, and DA9215 via Control Interface after the tEN delay needed for internal circuit start up.

If BUCKA_EN or BUCKB_EN is asserted when DA9213, DA9214, and DA9215 is in ON Mode the power up of

the related buck converter is initiated. If the bucks are controlled via GPI, the level of the controlling ports is

checked when entering ON mode, so that an active level will immediately have effect on the buck. If BUCKA_EN

or BUCKB_EN are not asserted and all controlling GPI ports are inactive, the buck converter will stay off with the

output pull down resistor enabled/disabled according to the setting of BUCKA_PD_DIS and BUCKB_PD_DIS.

5.3.2

OFF Mode

DA9213, DA9214, and DA9215 are in OFF Mode when the IC_EN port is lower than EN_OFF. In OFF Mode, the

bucks are always disabled and the output pull down resistors are disabled independently of BUCKA_PD_DIS

and BUCKB_PD_DIS. All I/O ports of DA9213, DA9214, and DA9215 are configured as high impedance.

5.4

Control Interfaces

All the features of DA9213, DA9214, and DA9215 can be controlled by SW through a serial control interfaces.

The communication is selectable to be either a 2-WIRE (I2C compliant) or a 4-WIRE connection (SPI compliant)

via control IF_TYPE, which will be selected during the initial OTP read. If 4-WIRE is selected, the GPIO3 and

GPI4 are automatically configured as interface pins. Data is shifted into or out of DA9213, DA9214, and DA9215

under the control of the host processor, which also provides the serial clock. In a normal application case, the

interface is only configured once from OTP values, which are loaded during the initial start-up of DA9213,

DA9214, and DA9215.

DA9213, DA9214, and DA9215 reacts only on read/write commands where the transmitted register address

(using the actual page bits as a MSB address range extensions) is within 0x50 to 0x67, 0xD0 to DF, 0x140 to

0x14F and (read only) 0x200 to 0x27F. Host access to registers outside these ranges will be ignored. This

means there will be no acknowledge after receiving the register address in 2-WIRE Mode, and SO stays HI-Z in

4-WIRE Mode. During debug and production modes write access is available to page 4 (0x200 to 0x27F).

DA9213, DA9214, and DA9215 will react only on write commands where the transmitted register address is

0x00, 0x80, 0x100 to0x106. The host processor must read the content of those registers before writing, thereby

changing only the bit fields that are not marked as reserved (the content of the read back comes from the

compatible PMIC, for example DA9063).

If the STAND_ALONE bit is asserted (OTP bit), DA9213, DA9214, and DA9215 will also react to read

commands.

5.4.1

4-WIRE Communication

In 4-WIRE Mode the interface uses a chip-select line (nCS/nSS), a clock line (SK), data input (SI) and data

output line (SO).

The DA9213, DA9214, and DA9215 register map is split into four pages that each contain up to 128 registers.

The register at address zero on each page is used as a page control register. The default active page after turn

on includes registers 0x50 to 0x6F. Writing to the page control register changes the active page for all

subsequent read/write operations unless an automatic return to page 0 was selected by asserting bit REVERT.

Unless the REVERT bit was asserted after modifying the active page, it is recommended to read back the page

control register to ensure that future data exchange is accessing the intended registers.

All registers outside the DA9213, DA9214, and DA9215 range are write only, that is, the DA9213, DA9214, and

DA9215 will not answer to a read command and the data bus is tristate (they are implicitly directed to DA9063).

In particular the information contained in registers 0x105 and 0x106 is used by DA9213, DA9214, and DA9215

to configure the control interface. They must be the same as the main PMIC (DA9063), so that a write to those

registers configures both the main PMIC and DA9213, DA9214, and DA9215 at the same time. The default OTP

settings also need to be identical for a correct operation of the system.

The 4-WIRE interface features a half-duplex operation, that is, data can be transmitted and received within a

single 16-bit frame at enhanced clock speed (up to 14 MHz). It operates at the clock frequencies provided by the

host.

DA9213 Datasheet(PDF) 32 Page - Renesas Technology Corp

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