DA9213 datasheet(25/62 Pages) RENESAS

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DA9213, DA9214, DA9215 Datasheet

R16DS0598EJ0361 Rev.03.61

Nov 03, 2025

CFR0011-120-00

Page 25

DA9215 contains also two buck converters, Buck A capable of 15 A and Buck B capable of 5 A.

To improve the accuracy of the delivered voltage, each buck converter is able to support a differential sensing of

the configured voltage directly at the point of load via dedicated positive and negative sense pins.

Both Buck A and Buck B have two voltage registers each. One defines the normal output voltage, while the other

offers an alternative retention voltage. In this way different application power modes can easily be supported.

The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility

according to the specific host processor status in the application.

When a buck is enabled, its output voltage is monitored, and a power good signal indicates that the buck output

voltage has reached a level higher than the VTH(PG) threshold. The power good is lost when the voltage drops

below VTH(PG) - VHYS(PG), which is the level at which the signal is de-asserted. The power good signaling should

not be used in conjunction with fast start up rates, configured in BUCKx_UP_CTRL register fields and can be

individually masked during DVC transitions using the PGA_DVC_MASK and PGB_DVC_MASK bits. For each of

the buck converters the status of the power good indicator can be read back via I2C from the PWRGOOD_A and

PWRGOOD_B status bits. It can be also individually assigned to either GPIO2 or GPIO3 using

BUCKA_PG_SEL and BUCKB_PG_SEL. For correct functionality, the GPIO ports need to be configured as

output. An I2C write in GPIOx_MODE can overwrite the internal configuration so that a new update will be

automatically done only when the internal power good indicator changes status.

The buck converters are capable of supporting DVC transitions that occur:

▪ When the active and selected A-voltage or B-voltage is updated to a new target value.

▪ When the voltage selection is changed from the A-voltage to the B-voltage (or B-voltage to the A voltage)

using VBUCKA_SEL and VBUCKB_SEL.

The DVC controller operates in Pulse Width Modulation (PWM) mode with synchronous rectification. When the

host processor changes the output voltage, the voltage transition of each buck converter can be individually

signaled with a READY signal routed to either GPIO2 or GPIO3. The port has to be configured as GPO and

selected for the functionality via READYA_CONF or READYB_CONF. In contrast to the power good signal, the

READY only informs the host processor about the completion of the digital DVC ramp without confirming that the

target voltage has actually been reached.

The slew rate of the DVC transition is individually programmed for each buck converter at 10 mV per (4, 2, 1, or

0.5) µs via control bit SLEW_RATE_A and SLEW_RATE_B.

The typical supply current is in the order of 17 mA per phase (quiescent current and charge/discharge current)

and drops to <1 µA when the buck is turned off.

When the buck is disabled, a pull down resistor (typically 150 Ω) for each phase is activated depending of the

value stored in register bits BUCKA_PD_DIS and BUCKB_PD_DIS. Phases disabled using PHASE_SEL_A and

PHASE_SEL_B will not have any pull down. The pull-down resistor is always disabled at all phases when

DA9213, DA9214, and DA9215 are OFF.

5.1.1

Switching Frequency

The switching frequency is chosen to be high enough to allow the use of a small 0.22 µH inductor (see a

complete list of coils in the Application Information, section 6). The buck switching frequency can be tuned using

buck converter frequency in steps of 90 kHz and helps to mitigate possible disturbances to other HF systems in

the application.

DA9213 Datasheet(PDF) 25 Page - Renesas Technology Corp

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