DA9213, DA9214, DA9215 Datasheet

R16DS0598EJ0361 Rev.03.61

Nov 03, 2025

CFR0011-120-00

Page 5

7.1.1

Register Page Control ........................................................................................................... 44

7.1.2

Register Page 0..................................................................................................................... 44

7.1.3

Register Page 1..................................................................................................................... 49

7.1.4

Register Page 2..................................................................................................................... 53

8.

Package Outline Drawings.......................................................................................................................... 58

8.1

Package Marking ................................................................................................................................. 59

9.

Ordering Information................................................................................................................................... 60

Figures

Figure 1. DA9213 System Diagram ......................................................................................................................... 2

Figure 2. DA9214 System Diagram ......................................................................................................................... 3

Figure 3. DA9215 System Diagram ......................................................................................................................... 3

Figure 4. DA9213/14/15 66 WL-CSP Ball Map ....................................................................................................... 8

Figure 5. DA9213/14/15 66 VFBGA Ball Map ......................................................................................................... 9

Figure 6. 2-WIRE Bus Timing ................................................................................................................................ 18

Figure 7. 4-WIRE Bus Timing ................................................................................................................................ 19

Figure 8. 2 Phase Auto-Mode, 0 A to 10 A............................................................................................................ 20

Figure 9. 2 Phase Auto-Mode, 0 A to 10 A............................................................................................................ 20

Figure 10. 4 Phase Auto-Mode, 0 A to 20 A (Linear) ............................................................................................ 20

Figure 11. 4 Phase Auto-Mode, 0 A to 20 A (Logarithmic).................................................................................... 20

Figure 12. 4 Phase Auto-Mode, 0 A to 20 A.......................................................................................................... 20

Figure 13. 1, 2, 3, and 4 Phase Modes ................................................................................................................. 20

Figure 14. Interface of DA9213/14/15 with DA9063 and the Host Processor ....................................................... 21

Figure 15. Typical Application of DA9213 ............................................................................................................. 22

Figure 16. Typical Application of DA9214 ............................................................................................................. 23

Figure 17. Typical Application of DA9215 ............................................................................................................. 24

Figure 18. Concept of Control of the Buck’s Output Voltage................................................................................. 27

Figure 19. Resistive Divider from VOUT to FBAN................................................................................................. 28

Figure 20. GPIO Principle of Operation (Example Paths) ..................................................................................... 31

Figure 21. Schematic of 4-WIRE and 2-WIRE Power Manager Bus..................................................................... 33

Figure 22. 4-WIRE Host Write and Read Timing (nCS_POL = 0, CPOL = 0, CPHA = 0) .................................... 34

Figure 23. 4-WIRE Host Write and Read Timing (nCS_POL= 0, CPOL = 0, CPHA = 1) ..................................... 34

Figure 24. 4-WIRE Host Write and Read Timing (nCS_POL = 0, CPOL = 1, CPHA = 0) .................................... 35

Figure 25. 4-WIRE Host Write and Read Timing (nCS_POL = 0, CPOL = 1, CPHA = 1) .................................... 35

Figure 26. Timing of 2-WIRE START and STOP Condition .................................................................................. 37

Figure 27. 2-WIRE Byte Write (SDA Line)............................................................................................................. 37

Figure 28. Examples of 2-WIRE Byte Read (SDA Line) ....................................................................................... 37

Figure 29. Examples of 2-WIRE Page Read (SDA Line) ...................................................................................... 38

Figure 30. 2-WIRE Page Write (SDA Line) ........................................................................................................... 38

Figure 31. 2-WIRE Repeated Write (SDA Line) .................................................................................................... 38

Figure 32. DA9213/14/15 66 WL-CSP Package Outline Drawing......................................................................... 58

Figure 33. DA9213/14/15 66 VFBGA Package Outline Drawing .......................................................................... 59

Figure 34. Package Marking.................................................................................................................................. 59