C167CS datasheet(292/517 Pages) INFINEON

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C167CS

Derivatives

The High-Speed Synchronous Serial Interface

User’s Manual

12-9

V2.0, 2000-07

edge generated by the master may be already used to clock in the first data bit. So the

slave’s first data bit must already be valid at this time.

Note: On the SSC always a transmission and a reception takes place at the same time,

regardless whether valid data has been transmitted or received. This is different

e.g. from asynchronous reception on ASC0.

The initialization of the SCLK pin on the master requires some attention in order to

avoid undesired clock transitions, which may disturb the other receivers. The state of the

internal alternate output lines is ‘1’ as long as the SSC is disabled. This alternate output

signal is ANDed with the respective port line output latch. Enabling the SSC with an idle-

low clock (SSCPO = ‘0’) will drive the alternate data output and (via the AND) the port

pin SCLK immediately low. To avoid this, use the following sequence:

• select the clock idle level (SSCPO = ‘x’)

• load the port output latch with the desired clock idle level (P3.13 = ‘x’)

• switch the pin to output (DP3.13 = ‘1’)

• enable the SSC (SSCEN = ‘1’)

• if SSCPO = ‘0’: enable alternate data output (P3.13 = ‘1’)

The same mechanism as for selecting a slave for transmission (separate select lines or

special commands) may also be used to move the role of the master to another device

in the network. In this case the previous master and the future master (previous slave)

will have to toggle their operating mode (SSCMS) and the direction of their port pins (see

description above).

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