C167CS datasheet(289/517 Pages) INFINEON

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C167CS

Derivatives

The High-Speed Synchronous Serial Interface

User’s Manual

12-6

V2.0, 2000-07

The Data Width Selection supports the transfer of frames of any length, from 2-bit

“characters” up to 16-bit “characters”. Starting with the LSB (SSCHB = ‘0’) allows

communication e.g. with ASC0 devices in synchronous mode (C166 Family) or 8051 like

serial interfaces. Starting with the MSB (SSCHB = ‘1’) allows operation compatible with

the SPI interface.

Regardless which data width is selected and whether the MSB or the LSB is transmitted

first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the

LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for

transfer by the internal shift register logic. The unselected bits of SSCTB are ignored, the

unselected bits of SSCRB will be not valid and should be ignored by the receiver service

routine.

The Clock Control allows the adaptation of transmit and receive behavior of the SSC

to a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out

transmit data, while the other clock edge is used to latch in receive data. Bit SSCPH

selects the leading edge or the trailing edge for each function. Bit SSCPO selects the

level of the clock line in the idle state. So for an idle-high clock the leading edge is a

falling one, a 1-to-0 transition. Figure 12-3 is a summary.

Figure 12-3

Serial Clock Phase and Polarity Options

MCD01960

Last

Bit

Transmit Data

First

Bit

Latch Data

Shift Data

Pins

MTSR/MRST

Serial Clock

SCLK

SSCPO SSCPH

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