C167CS datasheet(286/517 Pages) INFINEON

286 / 517 page

C167CS

Derivatives

The High-Speed Synchronous Serial Interface

User’s Manual

12-3

V2.0, 2000-07

Bit

Function (Programming Mode, SSCEN = ‘0’)

SSCBM

SSC Data Width Selection

Reserved. Do not use this combination

1…15: Transfer Data Width is 2 … 16 bit (<SSCBM> + 1)

SSCHB

SSC Heading Control Bit

Transmit/Receive LSB First

Transmit/Receive MSB First

SSCPH

SSC Clock Phase Control Bit

Shift transmit data on the leading clock edge, latch on trailing edge

Latch receive data on leading clock edge, shift on trailing edge

SSCPO

SSC Clock Polarity Control Bit

Idle clock line is low, leading clock edge is low-to-high transition

Idle clock line is high, leading clock edge is high-to-low transition

SSCTEN

SSC Transmit Error Enable Bit

Ignore transmit errors

Check transmit errors

SSCREN

SSC Receive Error Enable Bit

Ignore receive errors

Check receive errors

SSCPEN

SSC Phase Error Enable Bit

Ignore phase errors

Check phase errors

SSCBEN

SSC Baudrate Error Enable Bit

Ignore baudrate errors

Check baudrate errors

SSCAREN

SSC Automatic Reset Enable Bit

No additional action upon a baudrate error

The SSC is automatically reset upon a baudrate error

SSCMS

SSC Master Select Bit

Slave Mode. Operate on shift clock received via SCLK

Master Mode. Generate shift clock and output it via SCLK

SSCEN

SSC Enable Bit = ‘0’

Transmission and reception disabled. Access to control bits

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