C167CS datasheet(370/517 Pages) INFINEON

370 / 517 page

C167CS

Derivatives

The Analog/Digital Converter

User’s Manual

18-13

V2.0, 2000-07

18.2

Conversion Timing Control

When a conversion is started, first the capacitances of the converter are loaded via the

respective analog input pin to the current analog input voltage. The time to load the

capacitances is referred to as sample time. Next the sampled voltage is converted to a

digital value in successive steps, which correspond to the resolution of the ADC. During

these phases (except for the sample time) the internal capacitances are repeatedly

charged and discharged via pins

VAREF and VAGND.

The current that has to be drawn from the sources for sampling and changing charges

depends on the time that each respective step takes, because the capacitors must reach

their final voltage level within the given time, at least with a certain approximation. The

maximum current, however, that a source can deliver, depends on its internal resistance.

The time that the two different actions during conversion take (sampling, and converting)

can be programmed within a certain range in the C167CS relative to the CPU clock. The

absolute time that is consumed by the different conversion steps therefore is

independent from the general speed of the controller. This allows adjusting the A/D

converter of the C167CS to the properties of the system:

Fast Conversion can be achieved by programming the respective times to their

absolute possible minimum. This is preferable for scanning high frequency signals. The

internal resistance of analog source and analog supply must be sufficiently low,

however.

High Internal Resistance can be achieved by programming the respective times to a

higher value, or the possible maximum. This is preferable when using analog sources

and supply with a high internal resistance in order to keep the current as low as possible.

The conversion rate in this case may be considerably lower, however.

The conversion time is programmed via the upper two bits of register ADCON. Bitfield

ADCTC (conversion time control) selects the basic conversion clock (

fBC), used for the

operation of the A/D converter. The sample time is derived from this conversion clock.

Table 18-2 lists the possible combinations. The timings refer to CPU clock cycles, where

tCPU = 1 / fCPU.

The limit values for

fBC (see data sheet) must not be exceeded when selecting ADCTC

and

fCPU.

Table 18-2

ADC Conversion Timing Control

ADCON.15|14

(ADCTC)

A/D Converter

Basic Clock

fBC

ADCON.13|12

(ADSTC)

Sample Time

fCPU / 4

tBC × 8

fCPU / 2

tBC × 16

fCPU / 16

tBC × 32

fCPU / 8

tBC × 64

C167CS Datasheet(PDF) 370 Page - Infineon Technologies AG

C167CS Datasheet(HTML) 370 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL