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C167CS Datasheet(PDF) 371 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 371 Page - Infineon Technologies AG |
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371 / 517 page  C167CS Derivatives The Analog/Digital Converter User’s Manual 18-14 V2.0, 2000-07 The time for a complete conversion includes the sample time tS, the conversion itself and the time required to transfer the digital value to the result register (2 tCPU) as shown in the example below. Note: The non-linear decoding of bit field ADCTC provides compatibility with 80C166 designs for the default value (‘00’ after reset). Converter Timing Example Assumptions: fCPU = 25 MHz (i.e. tCPU = 40 ns), ADCTC = ‘00’, ADSTC = ‘00’. Basic clock fBC = fCPU / 4 = 6.25 MHz, i.e. tBC = 160 ns. Sample time tS = tBC × 8 = 1280 ns. Conversion time tC = tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.76 µs. Note: For the exact specification please refer to the data sheet of the selected derivative. |
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