C167CS datasheet(374/517 Pages) INFINEON

374 / 517 page

C167CS

Derivatives

The On-Chip CAN Interface

User’s Manual

19-2

V2.0, 2000-07

Figure 19-1

Registers Associated with the CAN Module

The bit timing is derived from the XCLK and is programmable up to a data rate of

1 MBaud. The minimum CPU clock frequency to achieve 1 MBaud is

fCPU ≥ 8/16 MHz,

depending on the activation of the CAN module’s clock prescaler.

The CAN module uses two pins of Port 4 or of Port 8 to interface to a bus transceiver.

It provides Full CAN functionality on up to 15 full-sized message objects (8 data bytes

each). Message object 15 may be configured for Basic CAN functionality with a double-

buffered receive object.

Both modes provide separate masks for acceptance filtering which allows the

acceptance of a number of identifiers in Full CAN mode and also allows disregarding a

number of identifiers in Basic CAN mode.

All message objects can be updated independent from the other objects during

operation of the module and are equipped with buffers for the maximum message length

of 8 Bytes.

MCA04473

SYSCON

CSR

MCRn

XP0IC

Core Registers

Control Registers

(within each module)

Object Registers

(within each module)

Interrupt Control

CSR

Control / Status Register

PCIR

Port Control / Interrupt Register

BTR

Bit Timing Register

GMS

Global Mask Short

U/LGML

Global Mask Long

U/LMLM Last Message Mask

MCRn

Configuration Register of Message n

U/LARn

Arbitration Register of Message n

XP1IC

UARn

LARn

SYSCON

System Configuration Register

SYSCON3 Peripheral Management Control Reg.

DP4

Port 4 Direction Control Register

ODP4

Port 4 Open Drain Control Register

DP8

Port 8 Direction Control Register

ODP8

Port 8 Open Drain Control Register

XP0IC

CAN1 Interrupt Control Register

XP1IC

CAN2 Interrupt Control Register

Data

PCIR

BTR

GMS

U/LGML

U/LMLM

SYSCON3

DP4

ODP4

DP8

ODP8

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