C167CS datasheet(377/517 Pages) INFINEON

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C167CS

Derivatives

The On-Chip CAN Interface

User’s Manual

19-5

V2.0, 2000-07

Tx/Rx Shift Register

The Transmit/Receive Shift Register holds the destuffed bit stream from the bus line to

allow the parallel access to the whole data or remote frame for the acceptance match

test and the parallel transfer of the frame to and from the Intelligent Memory.

Bit Stream Processor

The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream

between the Tx/Rx Shift Register, the CRC Register, and the bus line. The BSP also

controls the EML and the parallel data stream between the Tx/Rx Shift Register and the

Intelligent Memory such that the processes of reception, arbitration, transmission, and

error signalling are performed according to the CAN protocol. Note that the automatic

retransmission of messages which have been corrupted by noise or other external error

conditions on the bus line is handled by the BSP.

Cyclic Redundancy Check Register

This register generates the Cyclic Redundancy Check (CRC) code to be transmitted

after the data bytes and checks the CRC code of incoming messages. This is done by

dividing the data stream by the code generator polynomial.

Error Management Logic

The Error Management Logic (EML) is responsible for the fault confinement of the CAN

device. Its counters, the Receive Error Counter and the Transmit Error Counter, are

incremented and decremented by commands from the Bit Stream Processor. According

to the values of the error counters, the CAN controller is set into the states

error active,

error passive and busoff.

The CAN controller is

error active, if both error counters are below the error passive limit of 128.

It is

error passive, if at least one of the error counters equals or exceeds 128.

It goes

busoff, if the Transmit Error Counter equals or exceeds the busoff limit of 256.

The device remains in this state, until the

busoff recovery sequence is finished.

Additionally, there is the bit EWRN in the Status Register, which is set, if at least one of

the error counters equals or exceeds the error warning limit of 96. EWRN is reset, if both

error counters are less than the error warning limit.

C167CS Datasheet(PDF) 377 Page - Infineon Technologies AG