C167CS datasheet(378/517 Pages) INFINEON

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C167CS

Derivatives

The On-Chip CAN Interface

User’s Manual

19-6

V2.0, 2000-07

Bit Timing Logic

This block (BTL) monitors the busline input CAN_RXD and handles the busline related

bit timing according to the CAN protocol.

The BTL synchronizes on a

recessive to dominant busline transition at Start of Frame

(hard synchronization) and on any further

recessive to dominant busline transition, if the

CAN controller itself does not transmit a

dominant bit (resynchronization).

The BTL also provides programmable time segments to compensate for the propagation

delay time and for phase shifts and to define the position of the

Sample Point in the bit

time. The programming of the BTL depends on the baudrate and on external physical

delay times.

Intelligent Memory

The Intelligent Memory (CAM/RAM Array) provides storage for up to 15 message

objects of maximum 8 data bytes length. Each of these objects has a unique identifier

and its own set of control and status bits. After the initial configuration, the Intelligent

Memory can handle the reception and transmission of data without further CPU actions.

Organization of Registers and Message Objects

All registers and message objects of the CAN controller are located in the special CAN

address area of 256 Bytes, which is mapped into segment 0 and uses addresses

00’EF00H through 00’EFFFH. All registers are organized as 16-bit registers, located on

word addresses. However, all registers may be accessed bytewise in order to select

special actions without effecting other mechanisms.

indicator. This results in unique register names.

Example: module indicator is C1 (CAN module 1), specific name is Control/Status

Note: The address map shown below lists the registers which are part of the CAN

controller. There are also C167CS specific registers that are associated with the

CAN module.

C167CS Datasheet(PDF) 378 Page - Infineon Technologies AG