C167CS datasheet(383/517 Pages) INFINEON

383 / 517 page

C167CS

Derivatives

The On-Chip CAN Interface

User’s Manual

19-11

V2.0, 2000-07

stage of interrupt processing, and (if required) restricting CPU accesses to the

CAN module until the anticipated updating is complete.

PCIR

Port Control / Interrupt Register

XReg (EF02H)

Reset Value: XXXXH

98765

43210

- reserved -

IPC

INTID

Bit

Function

INTID

Interrupt Identifier

This number indicates the cause of the interrupt (if pending).

00H

Interrupt Idle: There is no interrupt request pending.

01H

Status Change Interrupt: The CAN controller has updated (not

necessarily changed) the status in the Control Register. This can

refer to a change of the error status of the CAN controller (EIE is

set and BOFF or EWRN change) or to a CAN transfer incident

(SIE must be set), like reception or transmission of a message

(RXOK or TXOK is set) or the occurrence of a CAN bus error (LEC

is updated). The CPU may clear RXOK, TXOK, and LEC,

however, writing to the status partition of the Control Register can

never generate or reset an interrupt. To update the INTID value

the status partition of the Control Register must be read.

02H

Message 15 Interrupt: Bit INTPND in the Message Control

The last message object has the highest interrupt priority of all

message objects.1)

1) Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the

possibility to update INTID or to reset INTID to “00H” (idle state).

(02 + N)

Message N Interrupt: Bit INTPND in the Message Control

that a message interrupt code is only displayed, if there is no other

interrupt request with a higher priority.1)

Example: message 1: INTID = 03H, message 14: INTID = 10H

IPC

Interface Port Control (reset value = 111B, i.e. no port connection)

The encoding of bitfield IPC is described in Section 19.7.

Note: Bitfield IPC can be written only while bit CCE is set.

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