C167CS datasheet(385/517 Pages) INFINEON

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C167CS

Derivatives

The On-Chip CAN Interface

User’s Manual

19-13

V2.0, 2000-07

Note: This register can only be written, if the config. change enable bit (CCE) is set.

Hard Synchronization and Resynchronization

To compensate phase shifts between clock oscillators of different CAN controllers, any

CAN controller has to synchronize on any edge from recessive to dominant bus level if

the edge lies between a Sample Point and the next Synchronization Segment, and on

any other edge if it itself does not send a dominant level. If the Hard Synchronization is

enabled (at the Start of Frame), the bit time is restarted at the Synchronization Segment,

otherwise the Resynchronization Jump Width (SJW) defines the maximum number of

time quanta by which a bit time may be shortened or lengthened during one

Resynchronization. The current bit time is adjusted by

SJW = (SJW + 1) × tq

Note: SJW is the programmed numerical value from the respective field of the Bit Timing

BTR

Bit Timing Register

XReg (EF04H)

Reset Value: UUUUH

9876

543210

TSEG2

TSEG1

SJW

BRP

Bit

Function

BRP

Baud Rate Prescaler

For generating the bit time quanta the CPU frequency

fCPU is divided by

2(1 – CPS)

× (BRP + 1). See also the prescaler control bit CPS in register

CSR.

SJW

(Re)Synchronization Jump Width

Adjust the bit time by maximum (SJW + 1) time quanta for

resynchronization.

TSEG1

Time Segment before sample point

There are (TSEG1 + 1) time quanta before the sample point.

Valid values for TSEG1 are “2 … 15”.

TSEG2

Time Segment after sample point

There are (TSEG2 + 1) time quanta after the sample point.

Valid values for TSEG2 are “1 … 7”.

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