C167CS datasheet(384/517 Pages) INFINEON

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C167CS

Derivatives

The On-Chip CAN Interface

User’s Manual

19-12

V2.0, 2000-07

19.2.2

Configuration of the Bit Timing

According to the CAN protocol specification, a bit time is subdivided into four segments:

Sync segment, propagation time segment, phase buffer segment 1 and phase buffer

segment 2.

Each segment is a multiple of the time quantum

tq, with

tq = (BRP + 1) × 2

(1 – CPS)

× t

XCLK.

Note: The CAN module is connected to the CPU clock signal, therefore

tXCLK = tCPU.

The Synchronization Segment (Sync Seg) is always 1

tq long. The Propagation Time

Segment and the Phase Buffer Segment 1 (combined to TSeg1) define the time before

the sample point, while Phase Buffer Segment 2 (TSeg2) defines the time after the

sample point. The length of these segments is programmable (except Sync-Seg) via the

Bit Timing Register (BTR).

Note: For exact definition of these segments please refer to the CAN Protocol

Specification.

Figure 19-4

Bit Timing Definition

The bit time is determined by the XBUS clock period

XCLK

, the Baud Rate Prescaler,

and the number of time quanta per bit:

bit time

Sync-Seg

TSeg1

TSeg2

[19.1]

Sync-Seg

= 1

× t

TSeg1

= (TSEG1 + 1)

× t

TSeg2

= (TSEG2 + 1)

× t

= (BRP + 1)

× 2(1-CPS) × t

XCLK

[19.2]

Note: TSEG1, TSEG2, and BRP are the programmed numerical values from the

respective fields of the Bit Timing Register.

MCT04393

Sync-

Seg

1 time quantum

(

TSeg1

Sample Point

Sync-

Seg

TSeg2

Transmit Point

1 Bit Time

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