C167CS datasheet(186/517 Pages) INFINEON

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C167CS

Derivatives

Dedicated Pins

User’s Manual

8-2

V2.0, 2000-07

At the end of a true single-chip mode reset (EA = ‘1’) the current level on pin ALE is

latched and is used for configuration (together with pin RD). Pin ALE selects standard

start/boot, when driven low (default) or alternate start/boot when driven high.

For standard configuration pin ALE should be low or not connected.

The External Read Strobe RD controls the output drivers of external memory or

peripherals when the C167CS reads data from these external devices. During accesses

to on-chip X-Peripherals RD remains inactive (high).

During reset an internal pullup ensures an inactive (high) level on the RD output.

At the end of reset the current level on pin RD is latched and is used for configuration.

For a reset with external access (EA = ‘0’) pin RD controls the oscillator watchdog. The

latched RD level determines the reset value of bit OWDDIS in register SYSCON. The

default high level on pin RD leaves the oscillator watchdog active (OWDDIS = ‘0’), while

a low level disables the watchdog (OWDDIS = ‘1’) e.g. for testing purposes.

For a true single-chip mode reset (EA = ‘1’) pin RD enables the bootstrap loader, when

driven low (pin ALE is evaluated together with pin RD).

For standard configuration pin RD should be high or not connected.

The External Write Strobe WR/WRL controls the data transfer from the C167CS to an

external memory or peripheral device. This pin may either provide an general WR signal

activated for both byte and word write accesses, or specifically control the low byte of an

external 16-bit device (WRL) together with the signal WRH (alternate function of P3.12/

BHE). During accesses to on-chip X-Peripherals WR/WRL remains inactive (high).

During reset an internal pullup ensures an inactive (high) level on the WR/WRL output.

The Ready Input READY receives a control signal from an external memory or

peripheral device that is used to terminate an external bus cycle, provided that this

function is enabled for the current bus cycle. READY may be used as synchronous

READY or may be evaluated asynchronously. When waitstates are defined for a READY

controlled address window the READY input is not evaluated during these waitstates.

An internal pullup ensures an inactive (high) level on the READY input.

The External Access Enable Pin EA determines if the C167CS after reset starts

fetching code from the internal ROM area (EA = ‘1’) or via the external bus interface

(EA = ‘0’). Be sure to hold this input low for ROMless devices. At the end of the internal

reset sequence the EA signal is latched together with the configuration (PORT0, RD,

ALE).

The Non-Maskable Interrupt Input NMI allows to trigger a high priority trap via an

external signal (e.g. a power-fail signal). It also serves to validate the PWRDN instruction

that switches the C167CS into Power-Down mode. The NMI pin is sampled with every

CPU clock cycle to detect transitions.

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