C167CS datasheet(216/517 Pages) INFINEON

216 / 517 page

C167CS

Derivatives

The External Bus Interface

User’s Manual

9-28

V2.0, 2000-07

Note: RP0H is initialized during the reset configuration and permits to check the current

configuration.

This configuration (except for bit WRC) can be changed via register RSTCON

(see Section 20.5).

RP0H

Reset Value of P0H

SFR (F108H/84H)

Reset Value: - - XXH

9876

543210

CLKCFG

SALSEL

CSSEL

WRC

Bit

Function

WRC

Write Configuration

Pins WR and BHE operate as WRL and WRH signals

Pins WR and BHE operate as WR and BHE signals

CSSEL

Chip Select Line Selection (Number of active CS outputs)

00:

3 CS lines: CS2 …CS0

01:

2 CS lines: CS1 … CS0

10:

No CS lines at all

11:

5 CS lines: CS4 …CS0 (Default without pulldowns)

SALSEL

Segment Address Line Selection (nr. of active segment addr. outputs)

00:

4-bit segment address: A19 … A16

01:

No segment address lines at all

10:

8-bit segment address: A23 … A16

11:

2-bit segment address: A17 … A16 (Default without pulldowns)

CLKCFG

Clock Generation Mode Configuration

These pins define the clock generation mode, i.e. the mechanism how the

internal CPU clock is generated from the externally applied (XTAL) input

clock.

C167CS Datasheet(PDF) 216 Page - Infineon Technologies AG

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