C167CS datasheet(220/517 Pages) INFINEON

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C167CS

Derivatives

The External Bus Interface

User’s Manual

9-32

V2.0, 2000-07

Arbitration Sequences

An external master may request the C167CS’s bus via the HOLD input. After completing

the currently running bus cycle the C167CS acknowledges this request via the HLDA

output and will then float its bus lines (internal pullups at CSx, RD, and WR, internal

pulldown at ALE). The new master may now access the peripheral devices or memory

banks via the same interface lines as the C167CS. During this time the C167CS can

keep on executing, as long as it does not need access to the external bus. All actions

that just require internal resources like instruction or data memory and on-chip generic

peripherals, may be executed in parallel.

Note: The XBUS is an internal representation of the external bus interface. Accesses to

XBUS peripherals use the EBC and therefore also cannot be executed during the

bus hold state.

When the C167CS needs access to its external bus while it is occupied by another bus

master, it demands it via the BREQ output. The arbiter can then remove the current

master from the bus. This is indicated to the C167CS by deactivating its HOLD input.

The C167CS responds by deactivating its HLDA signal, and then taking control of the

external bus itself. Of course also the request signal BREQ is deactivated after getting

control of the bus back.

Table 9-8

Interface Pins for Bus Arbitration

Function Direction Operational Description

P6.5 HOLD

INput

The hold request signal requests the external bus system

from the C167CS.

P6.6 HLDA

(Master

mode)

OUTput

The hold acknowledge signal acknowledges a hold

request and indicates to the external partners that the

C167CS has withdrawn from the bus and another

external bus master may now use it.

BGR1)

(Slave

mode)

INput

The bus grant signal indicates to the C167CS (slave) that

the master has withdrawn from the external bus in

response to the slave’s BREQ. The slave may now use

the external bus system until the master requests it back.

P6.7 BREQ

OUTput

The bus request signal indicates to the bus arbiter logic

that the C167CS requires control over the external bus,

which has been released and is currently controlled by

another bus master.

1) In slave mode pin HLDA inverts its direction to input. The changed functionality is indicated through the

different name.

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