C167CS datasheet(224/517 Pages) INFINEON

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C167CS

Derivatives

The External Bus Interface

User’s Manual

9-36

V2.0, 2000-07

In Slave Mode the C167CS inverts the direction of its HLDA pin and uses it as the bus

grant input BGR, while the master’s HLDA pin remains an output. This permits the direct

connection of these two signals without any additional glue logic for bus arbitration. The

BREQ outputs are mutually connected to the other partner’s HOLD input (see

Figure 9-15).

Figure 9-15

Sharing External Resources Using Slave Mode

Slave Mode is selected by intentionally switching pin BREQ to output (DP6.7 = ‘1’).

Normally the port direction register bits for the arbitration interface pins retain their reset

value which is ‘0’. Clearing bit DP6.7 (or preserving the reset value) selects Master

Mode, where the device operates compatible with earlier versions without the slave

mode feature.

Note: If the C167CS operates in slave mode and executes a loop out of external memory

which fits completely into the jump cache (e.g. JB bitaddr, $) its BREQ output may

toggle (period = 2 CPU clock cycles). BREQ is activated by the prefetcher that

wants to read the next sequential intstruction. BREQ is the deactivated, because

the target of the taken jump is found in the jump cache. A loop of a minimum length

of 3 words avoids this.

MCS04370

C167CR

in Master Mode

C167CR

in Slave Mode

Ext. Bus

HOLD

HLDA

BREQ

HOLD

BRG

BREQ

The pullups provide correct signal levels during the initialization phase.

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