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XC2000 Datasheet(PDF) 29 Page - Infineon Technologies AG

Part # XC2000
Description  16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 2 (of 2): Peripheral Units
PDF  729 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC2000 Datasheet(HTML) 29 Page - Infineon Technologies AG

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XC2000 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Preliminary
User’s Manual
14-11
V1.0, 2007-06
GPT_X7, V2.0
Incremental Interface Mode
Incremental interface mode for the core timer T3 is selected by setting bitfield T3M in
register T3CON to 110
B or 111B. In incremental interface mode, the two inputs
associated with core timer T3 (T3IN, T3EUD) are used to interface to an incremental
encoder. T3 is clocked by each transition on one or both of the external input pins to
provide 2-fold or 4-fold resolution of the encoder input.
Figure 14-7
Block Diagram of Core Timer T3 in Incremental Interface Mode
Bitfield T3I in control register T3CON selects the triggering transitions (see Table 14-3).
The sequence of the transitions of the two input signals is evaluated and generates count
pulses as well as the direction signal. So T3 is modified automatically according to the
speed and the direction of the incremental encoder and, therefore, its contents always
represent the encoder’s current position.
The interrupt request (T3IRQ) generation mode can be selected: In Rotation Detection
Mode (T3M = 110
B), an interrupt request is generated each time the count direction of
T3 changes. In Edge Detection Mode (T3M = 111
B), an interrupt request is generated
each time a count edge for T3 is detected. Count direction, changes in the count
direction, and count requests are monitored by status bits T3RDIR, T3CHDIR, and
T3EDGE in register T3CON.
MCB05394
Count
T3EUD
T3
EDGE
T3
RDIR
MUX
0
1
=1
T3UD
T3UDE
Change
Detect
T3CH
DIR
T3M
T3M
>1
_
Phase
Detect
T3R
T3IN
T3I
T3IRQ
Core
Timer T3
Toggle
Latch
T3OUT
to
T2/T4
Edge
Select



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