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XC2000 Datasheet(PDF) 40 Page - Infineon Technologies AG

Part # XC2000
Description  16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 2 (of 2): Peripheral Units
PDF  729 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC2000 Datasheet(HTML) 40 Page - Infineon Technologies AG

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XC2000 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Preliminary
User’s Manual
14-22
V1.0, 2007-06
GPT_X7, V2.0
Timer Concatenation
Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode
concatenates the core timer T3 with the respective auxiliary timer. This concatenation
forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T3OTL
is selected to clock the auxiliary timer.
• 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL are used
to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the
core timer T3. Thus, the two timers form a 32-bit timer.
• 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected
to clock the auxiliary timer, this timer is clocked on every second overflow/underflow
of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer + T3OTL
+ 16-bit auxiliary timer).
As long as bit T3OTL is not modified by software, it represents the state of the internal
toggle latch, and can be regarded as part of the 33-bit timer.
The count directions of the two concatenated timers are not required to be the same.
This offers a wide variety of different configurations.
T3, which represents the low-order part of the concatenated timer, can operate in timer
mode, gated timer mode or counter mode in this case.
Figure 14-15 Concatenation of Core Timer T3 and an Auxiliary Timer
MCA05399
Toggle Latch
T3OUT
T3IRQ
Count
T3R
Core Timer T3
Operating
Mode
Control
BPS1
TxI
T3IN
f
GPT
Auxiliary
Timer Tx
TxI
0
1
MUX
TxI.2
TxIN
TxIRQ
Up/Down
Up/Down
Count
MUX
TxRC
TxR
T3R
0
1
x = 2, 4
Edge
Select



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