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XC2000 Datasheet(PDF) 97 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 97 Page - Infineon Technologies AG |
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97 / 729 page  XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Analog to Digital Converter Preliminary User’s Manual 16-3 V1.0, 2007-06 ADC, UM_V0.1D6 16.1.2 Feature Set Features of each ADC kernel: • Analog supply voltage range from 3.3 V (minimum) to 5 V (nominal) for VDDPA • Input voltage range from 0 V to analog supply voltage VDDPA • Input multiplexer for a maximum of 16 possible analog input channels • Performance for 10-bit resolution (@ fADCI =16MHz): - conversion time less than 1.5 µs, ±2 LSB 10 TUE 1) @ supply voltage V DDPA =5 V - conversion time about 1.5 µs, tbd LSB 10 TUE @ supply voltage VDDPA = 3.3V • One standard reference input (VAREF) and one alternative reference input (CH0) available • 3 conversion request sources for external or timer-driven events, auto-scan, programmable sequences, SW-driven conversions, etc. • Synchronization of the ADC kernels for concurrent conversion starts and parallel sampling and measuring of analog input signals, e.g. for phase current measurements in AC drives • Control capability for an external analog multiplexer, respecting the additional set up time • Adjustable sampling times to accommodate output impedance of different analog signal sources (sensors, etc.) • Possibility to cancel running conversions on demand with automatic restart • Flexible interrupt generation (possibility of PEC support) • Limit checking to reduce interrupt load (e.g. for temperature measurements or overload detection, only values exceeding a programmable level lead to an interrupt) • Programmable data reduction filter, e.g. for digital anti-aliasing filtering, by adding a programmable number of conversion results • Independent result registers (8 independent registers) • Support of conversion result FIFO mechanism to allow a longer interrupt latency • Support of suspend and power saving modes • Individually programmable reference selection for each channel, e.g. to allow measurements of 3.3 V and 5 V signals in the full measurement range with the same ADC kernel 1) This value reflects the ADC module capability in an adapted electrical environment, e.g. characterized by “clean” routing of analog and digital signals and separation of analog and digital PCB areas, low noise on analog power supply (< 30 mV), low switching activity of digital pins near to the ADC, etc. |
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