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XC2000 Datasheet(PDF) 22 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 22 Page - Infineon Technologies AG |
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22 / 729 page ![]() XC2000 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Preliminary User’s Manual 14-4 V1.0, 2007-06 GPT_X7, V2.0 14.1.1 GPT1 Core Timer T3 Control The current contents of the core timer T3 are reflected by its count register T3. This register can also be written to by the CPU, for example, to set the initial start value. The core timer T3 is configured and controlled via its bitaddressable control register T3CON. GPT12E_T3CON Timer 3 Control Register SFR (FF42 H/A1H) Reset Value: 0000 H 15 14 13 12 11 10 98 76 543 210 T3 R DIR T3 CH DIR T3 ED GE BPS1 T3 OTL T3 OE T3 UDE T3 UD T3R T3M T3I rh rwh rwh rw rwh rw rw rw rw rw rw Field Bits Type Description T3RDIR 15 rh Timer T3 Rotation Direction Flag 0 Timer T3 counts up 1 Timer T3 counts down T3CHDIR 14 rwh Timer T3 Count Direction Change Flag This bit is set each time the count direction of timer T3 changes. T3CHDIR must be cleared by SW. 0 No change of count direction was detected 1 A change of count direction was detected T3EDGE 13 rwh Timer T3 Edge Detection Flag The bit is set each time a count edge is detected. T3EDGE must be cleared by SW. 0 No count edge was detected 1 A count edge was detected BPS1 [12:11] rw GPT1 Block Prescaler Control Selects the basic clock for block GPT1 (see also Section 14.1.5) 00 f GPT/8 01 f GPT/4 10 f GPT/32 11 f GPT/16 |
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