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XC2000 Datasheet(PDF) 59 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 59 Page - Infineon Technologies AG |
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59 / 729 page  XC2000 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Preliminary User’s Manual 14-41 V1.0, 2007-06 GPT_X7, V2.0 14.2.3 GPT2 Auxiliary Timer T5 Control Auxiliary timer T5 can be configured for timer mode, gated timer mode, or counter mode with the same options for the timer frequencies and the count signal as the core timer T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The contents of T5 may be captured to register CAPREL upon an external or an internal trigger. The start/stop function of the auxiliary timers can be remotely controlled by the T6 run control bit. Several timers may thus be controlled synchronously. The current contents of the auxiliary timer are reflected by its count register T5. This register can also be written to by the CPU, for example, to set the initial start value. The individual configurations for timer T5 are determined by its bitaddressable control register T5CON. Some bits in this register also control the function of the CAPREL register. Note that functions which are present in all timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers. Note: The auxiliary timer has no output toggle latch and no alternate output function. GPT12E_T5CON Timer 5 Control Register SFR (FF46 H/A3H) Reset Value: 0000 H 15 14 13 12 11 10 9 8765 432 10 T5 SC T5 CLR CI T5 CC CT3 T5 RC T5 UDE T5 UD T5R T5M T5I rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description T5SC 15 rw Timer 5 Capture Mode Enable 0 Capture into register CAPREL Disabled 1 Capture into register CAPREL Enabled T5CLR 14 rw Timer T5 Clear Enable Bit 0 Timer T5 is not cleared on a capture event 1 Timer T5 is cleared on a capture event |
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