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38D2 Datasheet(PDF) 114 Page - Renesas Technology Corp

Part # 38D2
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PDF  136 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

38D2 Datasheet(HTML) 114 Page - Renesas Technology Corp

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Rev.3.02
Apr 10, 2008
Page 114 of 131
REJ03B0177-0302
38D2 Group
NOTE:
1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [0FF116]) of UART control register is “0”.
NOTE:
1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [0FF116]) of UART control register is “0”.
Fig 96. Circuit for measuring output switching characteristics
Table 46 Switching characteristics (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta =
−20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ
Max.
tWH (SCLK)
Serial I/O1, 2 clock output “H” pulse width
tC(SCLK)/2
−30
ns
tWL (SCLK)
Serial I/O1, 2 clock output “L” pulse width
tC(SCLK)/2
−30
ns
td (SCLK-TXD)
Serial I/O1, 2 output delay time (1)
140
ns
tV (SCLK-TXD)
Serial I/O1, 2 output valid time (1)
−30
ns
tr (SCLK)
Serial I/O1, 2 clock output rising time
30
ns
tf (SCLK)
Serial I/O1, 2 clock output falling time
30
ns
Table 47 Switching characteristics (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta =
−20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ
Max.
tWH (SCLK)
Serial I/O1, 2 clock output “H” pulse width
tC(SCLK)/2
−80
ns
tWL (SCLK)
Serial I/O1, 2 clock output “L” pulse width
tC(SCLK)/2
−80
ns
td (SCLK-TXD)
Serial I/O1, 2 output delay time (1)
350
ns
tV (SCLK-TXD)
Serial I/O1, 2 output valid time (1)
−30
ns
tr (SCLK)
Serial I/O1, 2 clock output rising time
80
ns
tf (SCLK)
Serial I/O1, 2 clock output falling time
80
ns
Measurement output pin
100pF
CMOS output
Measurement output pin
100pF
N-channel open-drain output (Note)
1k
Ω
Note: When bit 4 of the UART control register
(address 001B16 [address 0FF116]) is “1.”
(N-channel open-drain output mode)
FLASH MEMORY VERSION



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