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38D2 Datasheet(PDF) 115 Page - Renesas Technology Corp |
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38D2 Datasheet(HTML) 115 Page - Renesas Technology Corp |
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115 / 136 page  Rev.3.02 Apr 10, 2008 Page 115 of 131 REJ03B0177-0302 38D2 Group Fig 97. Timing diagram (in single-chip mode) INT0 −INT2 CNTR0, CNTR1 0.2VCC tWL (INT) 0.8VCC tWH (INT) 0.2VCC 0.2VCC 0.8VCC 0.8VCC 0.2VCC tWL(XIN) 0.8VCC tWH(XIN) tc(XIN) XIN 0.2VCC 0.8VCC tw(RESET) tf tr 0.2VCC tWL(CNTR) 0.8VCC tWH(CNTR) tc(CNTR) td(SCLK-TXD) tV(SCLK-TXD) tC(SCLK) tWL(SCLK)tWH(SCLK) th(SCLK-RXD) tsu(RXD-SCLK) TXD1 TXD2 RXD1 RXD2 SCLK1 SCLK2 RESET FLASH MEMORY VERSION |
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