7545 datasheet(20/62 Pages) RENESAS

20 / 62 page

Rev.1.06

Mar 07, 2008

Page 20 of 59

REJ03B0140-0106

7545 Group

Interrupts

The 7545 group interrupts are vector interrupts with a fixed

priority scheme, and generated by 7 sources 3 external, 3

internal, and 1 software.

The interrupt sources, vector addresses(1), and interrupt priority

are shown in Table 9.

Each interrupt except the BRK instruction interrupt has the

interrupt request bit and the interrupt enable bit. These bits and

the interrupt disable flag (I flag) control the acceptance of

interrupt requests. Figure 16 shows an interrupt control diagram.

An interrupt requests is accepted when all of the following

conditions are satisfied:

• Interrupt disable flag ................................ “0”

• Interrupt request bit .................................. “1”

• Interrupt enable bit ................................... “1”

Though the interrupt priority is determined by hardware, priority

processing can be performed by software using the above bits

and flag.

NOTES:

1. Vector addressed contain interrupt jump destination addresses.

2. Reset function in the same way as an interrupt with the highest priority.

Table 9

Interrupt vector address and priority

Interrupt source

Priority

Vector addresses(1)

Interrupt request generating conditions

Remarks

High-

order

Low-

order

Reset (2)

1FFFD16

FFFC16

At reset input

Non-maskable

Key-on wakeup

FFFB16

FFFA16

AND operation of input logic level of port P0 (input) External interrupt

INT0

FFF916

FFF816

At detection of either rising or falling edge of INT0

input

External interrupt

(active edge selectable)

INT1

FFF716

FFF616

At detection of either rising or falling edge of INT1

input

External interrupt

(active edge selectable)

Timer 2

FFF516

FFF416

At timer 2 underflow

Timer 3

FFF316

FFF216

At timer 3 underflow

Timer 1

FFF116

FFF016

At timer 1 underflow

STP release timer underflow

BRK instruction

FFDD16

FFDC16

At BRK instruction execution

Non-maskable software interrupt

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