SH7201 datasheet(136/1196 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 108 of 1164

REJ09B0321-0200

5.7.2

Trap Instructions

When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU

operates as follows:

1. The exception service routine start address which corresponds to the vector number specified

in the TRAPA instruction is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

5.7.3

Slot Illegal Instructions

An instruction placed immediately after a delayed branch instruction is said to be placed in a delay

slot. When the instruction placed in the delay slot is undefined code, an instruction that rewrites

the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction,

slot illegal exception handling starts when such kind of instruction is decoded. The CPU operates

as follows:

1. The exception service routine start address is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the

delayed branch instruction immediately before the undefined code, the instruction that rewrites

the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU

instruction.

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

5.7.4

General Illegal Instructions

When undefined code placed anywhere other than immediately after a delayed branch instruction

(delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles

general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot

illegal instructions, however, the program counter value stored is the start address of the undefined

code.

SH7201 Datasheet(PDF) 136 Page - Renesas Technology Corp