SH7201 datasheet(133/1196 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 105 of 1164

REJ09B0321-0200

5.6.2

Interrupt Priority Level

The interrupt priority order is predetermined. When multiple interrupts occur simultaneously

(overlap), the interrupt controller (INTC) determines their relative priorities and starts processing

according to the results.

The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest

and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is

always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels

of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely

using the interrupt priority registers 01, 02, and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16) of

the INTC as shown in table 5.9. The priority levels that can be set are 0 to 15. Level 16 cannot be

set. See section 6.3.1, Interrupt Priority Registers 01, 02, 05 to 16 (IPR01, IPR02, IPR05 to

IPR16), for details of IPR01, IPR02, and IPR05 to IPR16.

Table 5.9

Interrupt Priority Order

Type

Priority Level

Comment

NMI

Fixed priority level. Cannot be masked

User break

Fixed priority level

H-UDI

Fixed priority level

IRQ

0 to 15

PINT

Set with interrupt priority registers 01, 02, and 05

to 16 (IPR01, IPR02, and IPR05 to IPR16)

On-chip peripheral module

0 to 15

Set with interrupt priority registers 01, 02, and 05

to 16 (IPR01, IPR02, and IPR05 to IPR16)

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