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SH7201 Datasheet(PDF) 160 Page - Renesas Technology Corp

Part # SH7201
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1196 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7201 Datasheet(HTML) 160 Page - Renesas Technology Corp

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Section 6 Interrupt Controller (INTC)
Rev. 2.00 Sep. 07, 2007 Page 132 of 1164
REJ09B0321-0200
6.3.13
DMA Transfer Request Enable Register 3 (DREQER3)
DMA transfer request enable register 3 (DREQER3) is an 8-bit readable/writable register that
enables/disables the ADC, MTU2 (channels 0 to 4), and RCAN-ET (channels 0 and 1) DMA
transfer requests, and enables/disables CPU interrupt requests.
DMA transfer request enable register 3 is initialized by a power-on reset or in deep standby mode.
0
1
2
3
4
5
6
7
00
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADC
MTU2
4ch
MTU2
3ch
MTU2
2ch
MTU2
1ch
MTU2
0ch
RCAN-ET
1ch
RCAN-ET
0ch
Bit:
Initial value:
R/W:
Bit
Bit Name
Initial
Value
R/W
Description
7
ADC
0
R/W
6
MTU2 4ch
0
R/W
5
MTU2 3ch
0
R/W
4
MTU2 2ch
0
R/W
3
MTU2 1ch
0
R/W
2
MTU2 0ch
0
R/W
1
RCAN-ET 1ch
0
R/W
0
RCAN-ET 0ch
0
R/W
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
request enabled
1: DMA transfer request enabled, CPU interrupt request
disabled



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