HD64F36022 datasheet(240/384 Pages) RENESAS

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Section 13 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Sep. 23, 2005 Page 214 of 354

REJ09B0025-0400

13.7

Interrupts

SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive

data full, and receive errors (overrun error, framing error, and parity error). Table 13.7 shows the

interrupt sources.

Table 13.7

SCI3 Interrupt Requests

Interrupt Requests

Abbreviation

Interrupt Sources

Receive Data Full

RXI

Setting RDRF in SSR

Transmit Data Empty

TXI

Setting TDRE in SSR

Transmission End

TEI

Setting TEND in SSR

Receive Error

ERI

Setting OER, FER, and PER in SSR

The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before

transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data

is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is

set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if

the transmit data has not been sent. It is possible to make use of the most of these interrupt

requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the

generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that

correspond to these interrupt requests to 1, after transferring the transmit data to TDR.

HD64F36022 Datasheet(PDF) 240 Page - Renesas Technology Corp