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SH7101 Datasheet(PDF) 335 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 335 Page - Renesas Technology Corp

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Section 10 Serial Communication Interface (SCI)
Rev.1.00 Sep. 18, 2008 Page 301 of 522
REJ09B0069-0100
10.4
Operation in Asynchronous Mode
Figure 10.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the communication line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver
are independent units, enabling full-duplex communication. Both the transmitter and the receiver
also have a double-buffered structure, so that data can be read or written during transmission or
reception, enabling continuous data transfer.
LSB
Start
bit
MSB
Idle state
(mark state)
Stop bit
0
Transmit/receive data
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1
1
Serial
data
Parity
bit
1 bit
1 or 2 bits
7 or 8 bits
1 bit
or
none
One unit of transfer data (character or frame)
Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
10.4.1
Data Transfer Format
Table 10.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 10.5, Multiprocessor Communication Function.



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