SH7101 datasheet(337/560 Pages) RENESAS

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Section 10 Serial Communication Interface (SCI)

Rev.1.00 Sep. 18, 2008 Page 303 of 522

REJ09B0069-0100

10.4.2

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.

In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs

internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of

the basic clock as shown in figure 10.3. Thus the reception margin in asynchronous mode is given

by formula (1) below.

M =

0.5 –

(D – 0.5)

–

– (L – 0.5) F

× 100% .......................... Formula (1)

Where

M: Reception margin (

N: Ratio of bit rate to clock (N = 16)

D: Clock duty cycle (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

Absolute value of clock rate deviation

Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula

below.

M = {0.5 – 1/(2

× 16)} × 100 [%] = 46.875%

However, this is only the computed value, and a margin of 20% to 30% should be allowed in

system design.

Internal basic

clock

16 clocks

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Start bit

Data sampling

timing

15 0

Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode

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