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SH7101 Datasheet(PDF) 447 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 447 Page - Renesas Technology Corp |
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447 / 560 page ![]() Section 14 Pin Function Controller (PFC) Rev.1.00 Sep. 18, 2008 Page 413 of 522 REJ09B0069-0100 (2) Port A Control Registers L3 to L1 (PACRL3 to PACRL1) in SH7109 Register Bit Bit Name Initial Value R/W Description PACRL3 PACRL1 PACRL1 15 15 14 PA15MD2 PA15MD1 PA15MD0 0 0 0 R/W R/W R/W PA15 Mode Select the function of the PA15/CK/ POE6/BACK pin. 000: PA15 I/O (port) 100: Setting prohibited 001: CK output (CPG) 101: BACK output (BSC) 010: POE6 input (port) 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 14 13 12 PA14MD2 PA15MD1 PA14MD0 0 0 0 R/W R/W R/W PA14 Mode Select the function of the PA14/ RD/POE5 pin. 000: PA14 I/O (port) 100: Setting prohibited 001: RD output (BSC) 101: Setting prohibited 010: POE5 input (port) 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 13 11 10 PA13MD2 PA13MD1 PA13MD0 0 0 0 R/W R/W R/W PA13 Mode Select the function of the PA13/ POE4/BREQ pin. 000: PA13 I/O (port) 100: Setting prohibited 001: Setting prohibited 101: BREQ input (BSC) 010: POE4 input (port) 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 12 9 8 PA12MD2 PA12MD1 PA12MD0 0 0 0 R/W R/W R/W PA12 Mode Select the function of the PA12/ WRL pin. 000: PA12 I/O (port) 100: Setting prohibited 001: WRL output (BSC) 101: Setting prohibited 010: Setting prohibited 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 11 7 6 PA11MD2 PA11MD1 PA11MD0 0 0 0 R/W R/W R/W PA11 Mode Select the function of the PA11/ ADTRG/SCK3 pin. 000: PA11 I/O (port) 100: Setting prohibited 001: Setting prohibited 101: SCK3 I/O (SCI) 010: ADTRG input (A/D) 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited |
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