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SH7101 Datasheet(PDF) 117 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 117 Page - Renesas Technology Corp |
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117 / 560 page  Section 6 Interrupt Controller (INTC) Rev.1.00 Sep. 18, 2008 Page 83 of 522 REJ09B0069-0100 IRQnS IRQnES ISR.IRQnF IRQ pins RESIRQn Level detection Edge detection SQ R CPU interrupt request (Acceptance of IRQn interrupt/Writing 0 after reading IRQnF = 1) Figure 6.2 Control of IRQ3 to IRQ0 Interrupts 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. As a different interrupt vector is assigned to each interrupt source, the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules by setting interrupt priority registers A, D to K (IPRA, IPRD to IPRK). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on- chip peripheral module interrupt that was accepted. |
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