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SH7101 Datasheet(PDF) 114 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 114 Page - Renesas Technology Corp |
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114 / 560 page  Section 6 Interrupt Controller (INTC) Rev.1.00 Sep. 18, 2008 Page 80 of 522 REJ09B0069-0100 6.3.4 Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) Interrupt priority registers are nine 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.2. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups, bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000.) Bit Bit Name Initial Value R/W Description 15 14 13 12 IPR15 IPR14 IPR13 IPR12 0 0 0 0 R/W R/W R/W R/W These bits set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 11 10 9 8 IPR11 IPR10 IPR9 IPR8 0 0 0 0 R/W R/W R/W R/W These bits set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) |
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