SH7101 datasheet(111/560 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev.1.00 Sep. 18, 2008 Page 77 of 522

REJ09B0069-0100

Bit

Bit Name

Initial

Value

R/W

Description

IRQ3S

R/W

IRQ3 Sense Select

Sets the IRQ3 interrupt request detection mode.

0: Interrupt request is detected at low level of IRQ3

input

1: Interrupt request is detected at edge of IRQ3 input

(edge direction is selected by ICR2)

3 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

6.3.2

Interrupt Control Register 2 (ICR2)

ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins

IRQ0

IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the

edge detection mode by the sense select bits of IRQ0 to IRQ 3 in the interrupt control register 1

(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the

setting of ICR2 is ignored.

Bit

Bit Name

Initial

Value

R/W

Description

IRQ0ES1

IRQ0ES0

R/W

These bits set the IRQ0 interrupt request edge detection

mode.

00: Interrupt request is detected at falling edge of

IRQ0

input

01: Interrupt request is detected at rising edge of

IRQ0

input

10: Interrupt request is detected at both falling and rising

edges of

IRQ0 input

11: Setting prohibited

IRQ1ES1

IRQ1ES0

R/W

These bits set the IRQ1 interrupt request edge detection

mode.

00: Interrupt request is detected at falling edge of

IRQ1

input

01: Interrupt request is detected at rising edge of

IRQ1

input

10: Interrupt request is detected at both falling and rising

edges of

IRQ1 input

11: Setting prohibited

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