SH7101 datasheet(108/560 Pages) RENESAS

108 / 560 page

Section 6 Interrupt Controller (INTC)

Rev.1.00 Sep. 18, 2008 Page 74 of 522

REJ09B0069-0100

Figure 6.1 shows a block diagram of the INTC.

IRQOUT

NMI

IRQ0

IRQ1

IRQ2

IRQ3

MTU

CMT

MMT

A/D

SCI

WDT

I/O

(Interrupt request)

Input

control

Com-

parator

Interrupt

request

CPU

I3 I2 I1 I0

Bus

interface

IPRA, IPRD to IPRK

ICR1

ISR

ICR2

Module bus

INTC

WDT:

Watchdog timer

I/O:

I/O port (Port output controller)

ICR1, ICR2:

Interrupt control register

ISR:

IRQ status register

IPRA, IPRD to IPRK:

Interrupt priority level setting registers A, D to K

SR:

Status register

IPR

MTU:

Multifunction timer pulse unit

CMT:

Compare match timer

MMT:

Motor management timer

A/D:

A/D converter

SCI:

Serial communication interface

Legend:

Figure 6.1 INTC Block Diagram

SH7101 Datasheet(PDF) 108 Page - Renesas Technology Corp

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