SH7101 datasheet(112/560 Pages) RENESAS

112 / 560 page

Section 6 Interrupt Controller (INTC)

Rev.1.00 Sep. 18, 2008 Page 78 of 522

REJ09B0069-0100

Bit

Bit Name

Initial

Value

R/W

Description

IRQ2ES1

IRQ2ES0

R/W

These bits set the IRQ2 interrupt request edge detection

mode.

00: Interrupt request is detected at falling edge of

IRQ2

input

01: Interrupt request is detected at rising edge of

IRQ2

input

10: Interrupt request is detected at both falling and rising

edges of

IRQ2 input

11: Setting prohibited

IRQ3ES1

IRQ3ES0

R/W

These bits set the IRQ3 interrupt request edge detection

mode.

00: Interrupt request is detected at falling edge of

IRQ3

input

01: Interrupt request is detected at rising edge of

IRQ3

input

10: Interrupt request is detected at both falling and rising

edges of

IRQ3 input

11: Setting prohibited

7 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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