SH7101 datasheet(121/560 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev.1.00 Sep. 18, 2008 Page 87 of 522

REJ09B0069-0100

6.6

Interrupt Operation

6.6.1

Interrupt Sequence

The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the

operations.

1. The interrupt request sources send interrupt request signals to the interrupt controller.

2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,

according to the priority levels set in interrupt priority level setting registers A, D to K (IPRA,

IPRD to IPRK). Interrupts that have lower-priority than that of the selected interrupt are

ignored.* If interrupts that have the same priority level or interrupts within a same module

occur simultaneously, the interrupt with the highest priority is selected according to the default

priority order indicated in table 6.2.

3. The interrupt controller compares the priority level of the selected interrupt request with the

interrupt mask bits (I3 to I0) in the CPU’s status register (SR). If the request priority level is

equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level

is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends

an interrupt request signal to the CPU.

4. When the interrupt controller accepts an interrupt, a low level is output from the

IRQOUT pin.

5. The CPU detects the interrupt request sent from the interrupt controller when CPU decodes the

instruction to be executed. Instead of executing the decoded instruction, the CPU starts

interrupt exception processing (figure 6.5).

6. SR and PC are saved onto the stack.

7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in

the status register (SR).

8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high

level is output from the

IRQOUT pin. When the accepted interrupt is sensed by edge, a high

level is output from the

IRQOUT pin at the moment when the CPU starts interrupt exception

processing instead of instruction execution as noted in (5) above. However, if the interrupt

controller accepts an interrupt with a higher priority than the interrupt just to be accepting, the

IRQOUT pin holds low level.

9. The CPU reads the start address of the exception service routine from the exception vector

table for the accepted interrupt, jumps to that address, and starts executing the program. This

jump is not a delay branch.

Note: *

Interrupt requests that are designated as edge-detect type are held pending until the

interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing

the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared

by a power-on reset or a manual reset.

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