SH7101 datasheet(122/560 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev.1.00 Sep. 18, 2008 Page 88 of 522

REJ09B0069-0100

Program

execution state

Interrupt?

NMI?

I3 to I0

≤

level 14?

Level 14

interrupt?

Level 1

interrupt?

I3 to I0

≤

level 13?

I3 to I0

level 0?

Yes

= low

Save SR to stack

Save PC to stack

Copy accept-interrupt

level to I3 to I0

= high

Read exception

vector table

Branch to exception

service routine

Level 15

interrupt?

Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU.

is the same signal as interrupt request signal to the CPU (see figure 6.1).

Therefore,

is output when the request priority level is higher than the level in bits I3 to I0 of SR.

When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when

the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).

However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted

and has output an interrupt request to the CPU, the

pin holds low level.

Figure 6.3 Interrupt Sequence Flowchart

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