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SH7101 Datasheet(PDF) 123 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 123 Page - Renesas Technology Corp |
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123 / 560 page ![]() Section 6 Interrupt Controller (INTC) Rev.1.00 Sep. 18, 2008 Page 89 of 522 REJ09B0069-0100 6.6.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. 32 bits 32 bits PC*1 SR Address 4n–8 4n–4 4n SP*2 Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always make sure that SP is a multiple of 4. Figure 6.4 Stack after Interrupt Exception Processing |
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