SH7101 datasheet(124/560 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev.1.00 Sep. 18, 2008 Page 90 of 522

REJ09B0069-0100

6.7

Interrupt Response Time

Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt

request until the interrupt exception processing starts and fetching of the first instruction of the

interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an

IRQ interrupt is accepted.

Table 6.3

Interrupt Response Time

Number of States

Item

NMI, Peripheral

Module

IRQ

Remarks

Idle cycle

0 or 1

Interrupt priority judgment

and comparison with SR

mask bits

Wait for completion of

sequence currently being

executed by CPU

X (

≥ 0)

The longest sequence is for

interrupt or address-error

exception processing (X = 4

+ m1 + m2 + m3 + m4). If an

interrupt-masking instruction

follows, however, the time

may be even longer.

Time from start of interrupt

exception processing until

fetch of first instruction of

exception service routine

starts

5 + m1 + m2 + m3

Performs the saving PC and

SR, and vector address

fetch.

Total: (7 or 8) + m1 +

m2 + m3 + X

9 + m1 + m2 +

m3 + X

Minimum:

0.25 to 0.3 µs at 40 MHz

Interrupt

response

time

Maximum:

12 + 2 (m1 + m2

+ m3) + m4

13 + 2 (m1 + m2

+ m3) + m4

0.48 µs* at 40 MHz

Notes: *

0.48 µs at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.

m1 to m4 are the number of states needed for the following memory accesses.

m1: SR save (longword write)

m2: PC save (longword write)

m3: Vector address read (longword read)

m4: Fetch first instruction of interrupt service routine

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