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SH7101 Datasheet(PDF) 190 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 190 Page - Renesas Technology Corp |
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190 / 560 page ![]() Section 8 Multifunction Timer Pulse Unit (MTU) Rev.1.00 Sep. 18, 2008 Page 156 of 522 REJ09B0069-0100 Bit Bit Name Initial value R/W Description 7 — 1 R Reserved This bit is always read as 1. The write value should always be 1. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective 5 N 0 R/W Reverse Phase Output (N) Control This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are on-output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are on- output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is carried out by external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings). 2 1 0 WF VF UF 0 0 0 R/W R/W R/W Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 8.28. |
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