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SH7101 Datasheet(PDF) 199 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 199 Page - Renesas Technology Corp |
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199 / 560 page  Section 8 Multifunction Timer Pulse Unit (MTU) Rev.1.00 Sep. 18, 2008 Page 165 of 522 REJ09B0069-0100 For details of PWM modes, see section 8.4.5, PWM Modes. TCNT0 to TCNT2 values H'0000 TIOCA_0 TIOCA_1 TGRB_0 Synchronous clearing by TGRB_0 compare match TGRA_2 TGRA_1 TGRB_2 TGRA_0 TGRB_1 TIOCA_2 Time Figure 8.12 Example of Synchronous Operation 8.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 8.29 shows the register combinations used in buffer operation. Table 8.29 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 3 TGRA_3 TGRC_3 TGRB_3 TGRD_3 4 TGRA_4 TGRC_4 TGRB_4 TGRD_4 |
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