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SH7101 Datasheet(PDF) 202 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 202 Page - Renesas Technology Corp |
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202 / 560 page  Section 8 Multifunction Timer Pulse Unit (MTU) Rev.1.00 Sep. 18, 2008 Page 168 of 522 REJ09B0069-0100 TCNT value H'09FB H'0000 TGRC Time H'0532 TIOCA TGRA H'0F07 H'0532 H'0F07 H'0532 H'0F07 H'09FB Figure 8.17 Example of Buffer Operation (2) 8.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 8.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 8.30 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 |
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