SH7101 datasheet(252/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 218 of 522

REJ09B0069-0100

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing

0 to it. When the DTC is activated, the flag is cleared automatically. Figure 8.68 shows the timing

for status flag clearing by the CPU.

Status flag

Write signal

Address

TSR address

Interrupt

request signal

TSR write cycle

Figure 8.68 Timing for Status Flag Clearing by the CPU

8.7

Usage Notes

8.7.1

Module Standby Mode Setting

MTU operation can be disabled or enabled using the module standby register. The initial setting is

for MTU operation to be halted. Register access is enabled by clearing module standby mode. For

details, refer to section 18, Power-Down Modes.

8.7.2

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower

pulse widths.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.69 shows the input clock

conditions in phase counting mode.

SH7101 Datasheet(PDF) 252 Page - Renesas Technology Corp